;	*****************************************************
TITLE	Am2900 FAMILY  C P U  MNEMONICS JAN 12, 1982 DEW
;	*****************************************************
;
;
; ******************************************
; Am2900 FAMILY MNEMONICS - AM29CPU.DEF FILE
; ******************************************
;
; This file was created to serve as a master cpu file.	The user must
; edit it as required for his/her particular application.
;
;
;
; Anyone finding errors in this file is requested to send a marked listing
; or portion thereof to:  AMD CUSTOMER EDUCATION CENTER
;			  490-A LAKESIDE DRIVE
;			  PO BOX 453  MS#71
;			  SUNNYVALE, CA  94086
;
;
; Advanced Micro Devices reserves the right to make changes in its product
; without notice in order to improve design and performance characteristics.
; The company assumes no responsibility for the use of any circuits or programs
; described herein.
EJECT
;
;
;
 WORD 64
;
; 13 DECEMBER 1976 JRM
; UPDATED SEPT 28, 1977
; UPDATED APRIL 16, 1981 DEW
; UPDATED MAY 15, 1981 DEW
; UPDATED JAN 12, 1982 DEW
;
;	INDEX:
;	Am2901 [1], [2], [3]
;	Am2914 [5]
;	Am2930 [6]
;	Am2932 [7]
;	Am2940 [8]
;	Am2903 [9], [10], [11], [12]
;	Am29203 [9], [11], [13], [14]
;	THREE-ADDRESS EXPANDED MEMORY SAMPLE [15], [16], [17], [18]
;	MISCELLANEOUS FIELDS
;		REGISTERS [R]
;		CARRY BIT (NOT Am2904) [19]
;	Am2910 [20]
;	Am29811 ADDED INSTRUCTION
;	Am2925 MICROPROGRAMMABLE CLOCK CYCLE SELECT + CONTROL LINES [21]
;	Am290 SHIFT EXAMPLES
;	Am2904 STATUS REGISTER EXAMPLES
;	Am2904 CONDITION CODE OUTPUT EXAMPLES
;	MORE MISCELLANEOUS FIELDS
;		OUTPUT ENABLE
;		INSTRUCTION ENABLE
;		CONDITION CODE MUX - DATA MONITOR PROBLEM ADDITION
;	EXAMPLES OF DEF STATEMENTS - TWO ADDRESS - NONEXPANDED MEMORY
EJECT
;
; * * * * * * * * * * * * * * * * * * * * * * * *
;
; Am2901 INSTRUCTION SET
;
; * * * * * * * * * * * * * * * * * * * * * * * *
;
; Am2901 SOURCE OPERANDS (R S)			[1]
;
AQ:	EQU	Q#0
AB:	EQU	Q#1
ZQ:	EQU	Q#2
ZB:	EQU	Q#3
ZA:	EQU	Q#4
DA:	EQU	Q#5
DQ:	EQU	Q#6
DZ:	EQU	Q#7
;
; Am2901 ALU FUNCTIONS (R FUNCTION S)		[2]
; *** TO USE: DELETE THE .01 AND DELETE THE Am2903/29203 INSTRUCTION SETS ***
;
ADD.01: 	EQU	Q#0
SUBR.01:	EQU	Q#1
SUBS.01:	EQU	Q#2
OR.01:		EQU	Q#3
AND.01: 	EQU	Q#4
NOTRS.01:	EQU	Q#5
EXOR.01:	EQU	Q#6
EXNOR.01:	EQU	Q#7
;
; Am2901 DESTINATION CONTROL			[3]
;
QREG.01:	EQU	Q#0
NOP.01: 	EQU	Q#1
RAMA.01:	EQU	Q#2
RAMF.01:	EQU	Q#3
RAMQD.01:	EQU	Q#4
RAMD.01:	EQU	Q#5
RAMQU.01:	EQU	Q#6
RAMU.01:	EQU	Q#7
;
EJECT
;
;
; EXAMPLE SUB STATEMENTS
;
ALU:	SUB	3VQ#0, 3VQ#0, 3VQ#1, 2VB#00	; Am2901 FIELDS ONLY
;		SOURCE FUNCT  DEST   CARRY
;
REGS:	SUB	4VH#0, 4VH#0			; ALU REGISTER ADDRESSES
;		RA     RB
;
SAMPLE: DEF	19X, ALU, REGS, 2VB#00, 24X	; USAGE OF SUB STATEMENTS
;		SEQ		MUX  etc.
;
; Although the file is written with DEF statements which include the
; very same fields, SUB statements are included here for a reference
; example.  The use of SUB statements to partially define a microword
; allows a SUB to be defined immediatly after the mnemonics of the
; individual fields.  The DEF statement may be defined after all of the
; SUB statements to which it refers are defined.  The DEF statements are then
; more readable. The comments which would appear with a DEF statement would
; then appear with the SUB statement (what the field is, what the default
; represents, etc.).  This file has been written with both versions to
; provide a reference.	Whichever method is chosen, DOCUMENT THE STATEMENTS.
;
; NOTE THAT, if the sequencer fields had been defined, the 19X above could
; have been replaced by the sequencer SUB statement name.
EJECT
;
; * * * * * * * * * * * * * * * *
;
; Am2914 INSTRUCTION SET			[5]
;
; * * * * * * * * * * * * * * * *
;
MCLR:	EQU	H#0	; MASTER CLEAR
CLRIN:	EQU	H#1	; CLEAR ALL INTERRUPTS
CLRMB:	EQU	H#2	; CLEAR INTERRUPTS FROM M-BUS
CLRMR:	EQU	H#3	; CLEAR INTERRUPTS FROM MASK REGISTER
CLRVC:	EQU	H#4	; CLEAR INTERRUPT FROM LAST VECTOR READ
RDVC:	EQU	H#5	; READ VECTOR
RDSTA:	EQU	H#6	; READ STATUS REGISTER
RDM:	EQU	H#7	; READ MASK REGISTER
SETM:	EQU	H#8	; SET MASK REGISTER
LDSTA:	EQU	H#9	; LOAD STATUS REGISTER
BCLRM:	EQU	H#A	; BIT CLEAR MASK REGISTER
BSETM:	EQU	H#B	; BIT SET MASK REGISTER
CLRM:	EQU	H#C	; CLEAR MASK REGISTER
DISIN:	EQU	H#D	; DISABLE INTERRUPT REQUEST
LDM:	EQU	H#E	; LOAD MASK REGISTER
ENIN:	EQU	H#F	; ENABLE INTERRUPT REQUEST
;
EJECT
; * * * * * * * * * * * * * * * * * *
;
; Am2930 PROGRAM CONTROL UNIT			[6]
;
; * * * * * * * * * * * * * * * * * *
;
; NON-CONDITIONAL INSTRUCTIONS
;
PRST:	EQU	5H#00:	; RESET
FPC:	EQU	5H#01:	; FETCH PC
FR:	EQU	5H#02:	; FETCH R
FD:	EQU	5H#03:	; FETCH D
FRD:	EQU	5H#04:	; FETCH R PLUS D
FPD:	EQU	5H#05:	; FETCH PC PLUS D
FPR:	EQU	5H#06:	; FETCH PC PLUS R
FSD:	EQU	5H#07:	; FETCH S PLUS D
FPLR:	EQU	5H#08:	; FETBH PC, LOAD R
FRDR:	EQU	5H#09:	; FETCH R PLUS D, LOAD R
PLDR:	EQU	5H#0A:	; LOAD R
PSHP:	E  5H#0B:  ; PUSH PC
PSHD:	EQU	5H#0C:	; PUSH D
POPS:	EQU	5H#0D:	; POP S
POPP:	EQU	5H#0E:	; POP PC
PHLD:	EQU	5H#0F:	; HOLD
;
; CONDITIONAL INSTRUCTIONS - FAIL TEST, EXECUTE FPC
;
JMPR:	EQU	5H#10:	; JUMP R
JMPD:	EQU	5H#11:	; JUMP D
JMPZ:	EQU	5H#12:	; JUMP ZERO
JPRD:	EQU	5H#13:	; JUMP R PLUS D
JPPD:	EQU	5H#14:	; JUMP PC PLUS D
JPPR:	EQU	5H#15:	; JUMP PC PLUS R
JSBR:	EQU	5H#16:	; JUMP SUBROUTINE R
JSBD:	EQU	5H#17:	; JUMP SUBROUTINE D
JSBZ:	EQU	5H#18:	; JUMP SUBROUTINE ZERO
JSRD:	EQU	5H#19:	; JUMP SUBROUTINE R PLUS D
JSPD:	EQU	5H#1A:	; JUMP SUBROUTINE PC PLUS D
JSPR:	EQU	5H#1B:	; JUMP SUBRUTINE PC PLUS R
RTS:	EQU	5H#1C:	; RETURN S
RTSD:	EQU	5H#1D:	; RETURN S PLUS D
CHLD:	EQU	5H#1E:	; HOLD
PSUS:	EQU	5H#1F:	; SUSPEND
;
EJECT
; * * * * * * * * * * * * * * * * * *
;
; Am2932 PROGRAM CONTROL UNIT			[7]
;
; * * * * * * * * * * * * * * * * * *
;
; TO USE: DELETE THE .32  FROM Am2932 MNEMONICS IF NEEDED
; AND DELETE THE Am2930 INSTRUCTION SET
;
PRST.32:	EQU	H#0	; RESET
PSUS.32:	EQU	H#1	; SUSPEND
PSHD.32:	EQU	H#2	; PUSH D
POPS.32:	EQU	H#3	; POP STACK
FPC.32: 	EQU	H#4	; FETCH PC
JMPD.32:	EQU	H#5	; JUMP D
PSHP.32:	EQU	H#6	; PUSH PC
RTS.32:        EQU     H#7     ; RETURN STACK
FR.32:		EQU	H#8	; FETCH R
FPR.32: 	EQU	H#9	; FETCH PC PLUS R
FPLR.32:	EQU	H#A	; FETCH PC, LOAD R
JMPR.32:	EQU	H#B	; JUMP R
JPPR.32:	EQU	H#C	; JUMP PC PLUS R
JSBR.32:	EQU	H#D	; JUMP SUBROUTINE R
JSPR.32:	EQU	H#E	; JUMP SUBROUTINE PC PLUS R
PLDR.32:	EQU	H#F	; LOAD R
EJECT
; * * * * * * * * * * * * * * * * * * *
;
; Am2940 DMA CONTROL UNIT			[8]
;
; * * * * * * * * * * * * * * * * * * *
; INSTRUCTIONS
;
WRCR:	EQU	Q#0	; WRITE CONTROL REGISTER
RDCR:	EQU	Q#1	; READ CONTROL REGISTER
RDWC:	EQU	Q#2	; READ WORD COUNTER
RDAC:	EQU	Q#3	; READ ADDRESS OUNTER
REIN:	EQU	Q#4	; REINITIALIZE COUNTERS
LDAD:	EQU	Q#5	; LOAD ADDRESS
LDWC:	EQU	Q#6	; LOAD WORD COUNT
ENCT:	EQU	Q#7	; ENABLE COUNTERS
;
; CONTROL MODE BYTE
; NOTE - BITS 3 THROUGH 7 ARE DON'T CARE
;
WC1I:	EQU	8Q#0%	; WORD COUNT EQUALS ONE, INCREMENT ADDRESS COUNTER
WCCI:	EQU	8Q#1%	; WORD COUNT COMPARE, INCREMENT ADDRESS COUNTER
ADCI:	EQU	8Q#2%	; ADDRESS COMPARE, INCREMENT ADDRESS COUNTER
WCOI:	EQU	8Q#3%	; WORD COUNTER CARRY OUT, INCREMENT ADDRESS COUNTER
WC1D:	EQU	8Q#4%	; WORD COUNT EQUALS ONE, DECREMENT ADDRESS COUNTER
WCCD:	EQU	8Q#5%	; WORD COUNT COMPARE, DECREMENT ADDRESS COUNTER
ADCD:	EQU	8Q#6%	; ADDRESS COMPARE, DECREMENT ADDRESS COUNTER
WCOD:	EQU	8Q#7%	; WORD COUNTER CARRY OUT, DECREMENT ADDRESS COUNTER
;
EJECT
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; Am2903 INSTRUCTION SET
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; ALU SOURCE OPERANDS (EA, I0, OEB)		[9]
; 16 REGISTER - TWO ADDRESS VERSION
;
; NOTE: USE FOR BOTH THE Am2903 AND THE Am29203 * * *
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
;
RAMAB:		EQU	Q#0		; RAM A PORT, RAM B PORT
RAMADB: 	EQU	Q#1		; RAM A PORT, DATA BUS B
RAMAQ:		EQU	Q#2		; OR Q#3 - RAM A PORT, Q REGISTE
DARAMB: 	EQU	Q#4		; DATA BUS A, RAM B PORT
DADB:		EQU	Q#5		; DATA BUS A, DATA BUS B
DAQ:		EQU	Q#6		; OR Q#7 - DATA BUS A, Q REGISTER
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; ALU FUNCTIONS - NORMAL MODE (I4, I3, I2, I1, I0 ALL NOT 0)
; Am2903 ONLY !  * * * TO USE, DELETE THE .03 AND TAG OR
; DELETE THE Am29203 FUNCTIONS * * *
;						[10]
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
SPECL.03:	EQU	H#0		; I0 MUST BE LOW
HIGH.03:	EQU	H#0		; I0 MUT BE HIGH (Q REGISTER SELECT)
SUBR.03:	EQU	H#1		; F = S - R - 1 + Cin
SUBS.03:	EQU	H#2		; F = R - S - 1 + Cin
ADD.03: 	EQU	H#3		; F = R + S + Cin
INCRS.03:	EQU	H#4		; F = S + Cin
INCSNON.03:	EQU    H#5	       ; F = NOT S + Cin
INCRR.03:	EQU	H#6		; F = R + Cin
INCRNON.03:	EQU	H#7		; F = NOT R + Cin
LOW.03: 	EQU	H#8		; F = LOW
NOTRS.03:	EQU	H#9		; F = NOT R AND S
EXNOR.03:	EQU	H#A		; F = R EXNOR S
EXOR.03:	EQU	H#B		; F = R EXOR S
AND.03: 	EQU	H#C		; F = R AND S
NOR.03: 	EQU	H#D		; F = R NOR S
NAND.03:	EQU	H#E		; F = R NAND S
OR.03:		EQU	H#F		; F = R OR S
EJECT
; * * * * * * * * * * * * * * * * * * * *
;
; ALU DESTINATION CONTROL ( I8 - I7 - I6 - I5)		[11]
;     NORMAL FUNCTIONS
;
; NOTE: USE FOR BOTH THE Am2903 AND THE Am29203 * * * *
;
; * * * * * * * * * * * * * * * * * * * * * * *
;
RAMDA:		EQU	H#0		; F TO RAM, ARITHMETIC DOWN SHIFT
RAMDL:		EQU	H#1		; F TO RAM, LOGICAL DOWN SHIFT
RAMQDA: 	EQU	H#2		; DOUBLE PRECISION ARITHMETIC DOWN SHIFT
RAMQDL: 	EQU	H#3		; DOUBLE PRECISION LOGICAL DOWN SHIFT
RAM:		EQU	H#4		; F TO RAM WITH PARITY
QD:		EQU	H#5		; F TO Y, DOWN SHIFT Q
LOADQ:		EQU	H#6		; F TO Q WITH PARITY
RAMQ:		EQU	H#7		; F TO RAM AND Q WITH PARITY
RAMUPA: 	EQU	H#8		; F TO RAM, ARITHMETIC UP SHIFT
RAMUPL: 	EQU	H#9		; F TO RAM, LOGICAL UP SHIFT
RAMQUPA:	EQU	H#A		; DOUBLE PRECISION ARITHMETIC UP SHIFT
RAMQUPL:	EQU	H#B		; DOUBLE PRECISION LOGICAL UP SHIFT
YBUS:		EQU	H#C		; F TO Y ONLY
QUP:		EQU	H#D		; F TO Y, UP SHIFT Q
SIGNEXT:	EQU	H#E		; SIO0 TO Yi
RAMEXT: 	EQU	H#F		; F TO Y, SIGN EXTEND LEAST SIG. BTE
EJECT
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; SPECIAL FUNCTIONS (I8-I7-I6-I5)		[12]
;
;
; Am2903 FUNCTIONS ONLY
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
MULT.03:	EQU	H#0		; UNSIGNED MULTIPLY
TWOMULT.03:	EQU	H#2		; TWO'S COMPLEMENT MULTIPLY
TWOLAST.03:	EQU	H#6		; TWO'S COMPLEMENT MULTIPLY LAST STEP
INCRMNT.03:	EQU	H#4		; INCREMENT BY 1 + Cin
SGNTWO.03:	EQU	H#5		; SIGN MAGNITUDE-TWO'S COMPL CONVERSION
SLN.03: 	EQU	H#8		; SINGLE LENGTH NORMALIZE
DLN.03: 	EQU	H#A		; DOUBLE LENGTH NORMALIZE
DIVFRST.03:	EQU	H#A		; TWO'S COMPLEMENT DIVIIRST STEP
DIVIDE.03:	EQU	H#C		; TWO'S COMPLEMENT DIVIDE MIDDLE STEPS
DIVLAST.03:	EQU	H#E		; TWO'S COMPLEMENT DIVIDE LAST STEP
;
EJECT
; **********************************************************************
; NEW!	 NEW!	NEW!   NEW!   NEW!   NEW!   NEW!   NEW!   NEW!	 NEW!
;
; Am29203 INSTRUCTION SET - 5/15/81 - DEW
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; Am29203 SOURCE SELECT - SEE Am2903 SOURCE SELECTION (SAME)
; TWO - ADDRESS OPERATION ONLY
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; Am29203 ALU FUNCTIONS - NORMAL MODE ( I4, I3, I2, I1, I0 ALL NOT 0 )
;						[13]
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; NOTE DIFFERENCE FROM Am2903 - ** FIVE ** INSTRUCTION FIELDS USED
; IN THE DATA SHEET TABLE - THEREFORE RESTRICTIONS ON THE SOURCE SELECTION
; APPLY.   THE FUNCTIONS ARE GROUPED ACCORDING TO THE RESTRICTION
;
;
; * * THE FOLLOWING DO NOT HAVE RESTRICTIONS ON THE SOURCE SELECTION * *
;
SUBR:		EQU	H#1		; Fi = Si - Ri - 1 + Cin
SUBS:		EQU	H#2		; Fi = Ri - Si - 1 + Cin
ADD:		EQU    H#3	       ; Fi = Ri + Si + Cin
INCRS:		EQU	H#4		; Fi = Si + Cin
INCRSNON:	EQU	H#5		; Fi = ~Si + Cin
NOTRS:		EQU	H#9		; Fi = NOT Ri AND Si
EXNOR:		EQU	H#A		; Fi = Ri EXNOR Si
EXOR:		EQU	H#B		; Fi = Ri EXOR Si
AND:		EQU	H#C		; Fi = Ri AND Si
NOR:		EQU	H#D		; Fi = Ri NOR Si
NAND:		EQU	H#E		; Fi = Ri NAND Si
OR:		EQU	H#F		; Fi = Ri OR Si
;
; * * THE FOLLOWING REQUIRE THAT RAMAQ OR DAQ BE THE SELECTED SOURCE * *
HIGH:		EQU	H#0		; Fi = HIGH
INCRR:		EQU	H#6		; Fi = Ri + Cin
INCRNON:	EQU	H#7		; Fi = ~Ri + Cin
LOW:		EQU	H#8		; Fi = LOW
;
; * * THE FOLLOWING REQUIRE THAT Q IS ** NOT ** IN THE SELECTED SOURCE * *
;
SPECL:		EQU	H#0		; SPECIAL FUNCTIONS
RESRVD.1:	EQU	H#6		; RESERVED FOR LATER USE
RESRVD.2:	EQU	H#7		; RESERVED FOR LATER USE
SPECIL.2:	EQU	H#8		; SPECIAL FUNCTIONS (MULTI-BCD)
EJECT
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; DESTINATION CONTROL - SEE Am2903 DESTINATION (SAME)
;
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *  * * * * *
;
; Am29203 SPECIAL FUNCTIONS			[14]
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; INSTRUCTION LINES I8, I7, I6, I5
;
; THE FOLLOWING ARE USED WITH SPECL:
;
MULT:		EQU	H#0	; UNSIGNED MULTIPLY
TWOMULT:	EQU	H#2	; TWO'S COMPLEMENT MULTIPLY
TWOLAST:	EQU	H#6	; TWO'S COMPLEMENT MULTIPLY - LAST STEP
DECRMNT:	EQU	H#3	; DECREMENT BY 1 OR 2
INCRMNT:	EQU	H#4	; INCREMENT BY 1 OR 2
SGNTWO: 	EQU	H#5	; SIGN MAGNITUDE-TWO'S COMPLEMENT CONVERSION
SLN:		EQU	H#8	; SINGLE LENGTH NORMALIZE
DLN:		EQU	H#A	; DOUBLE LENGTH NORMALIZE
DIVFRST:	EQU	HA     ; TWO'S COMPLEMENT DIVIDE - FIRST STEP
DIVIDE: 	EQU	H#C	; TWO'S COMPLEMENT DIVIDE - MIDDLE STEPS
DIVLAST:	EQU	H#E	; TWO'S COMPLEMENT DIVIDE - LAST STEP
BCD.BIN:	EQU	H#1	; BCD TO BINARY CONVERSION
BCD.DIV2:	EQU	H#7	; BCD DIVIDE BY TWO
BIN.BCD:	EQU	H#9	; BINARY TO BCD CONVERSION
BCD.ADD:	EQU	H#B	; BCD ADD
BCD.SUBS:	EQU	H#D	; BCD SUBTRACT Fi = Ri - Si - 1 + Cin [BCD]
BCD.SUBR:	EQU	H#F	; BCD SUBTRACT Fi = Si - Ri - 1 + Cin [BCD]
;
; THE FOLLOWING ARE USED WITH SPECIL.2:
;
MULTIBCD:	EQU	H#1	; MULTIPRECISION BCD TO BINARY CONVERSION
MULTIBIN:	EQU	H#9	; MULTIPRECISION BINARY TO BCD CONVERSION
;
EJECT
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
;
; DEFINITION FILE FOR FIGURE 29, PAGE 2-57, 1980 DATA BOOK
;
; EXPANDED MEMORY FOR THE Am2903 USING THE Am29705
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; ONLY THE SOURCE FIELDS CHANGE - EXPANDED
; A THIRD ADDRESS FIELD WAS ALSO ADDED (ADDRESS C)
;
;
;
; SOURCE OPERANDS			[15]
; ADDED A ADDRESS BITS (A6-A5-A4)
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
;
AINALU: EQU	Q#0		; A ADDRESSES 2903 REGISTERS
AIS7051:EQU	Q#1		; A ADDRESSES FIRST 29705 ADDITION
AIS7052:EQU	Q#2		; A ADDRESSES SECOND 29705 ADDITION
ACONST: EQU	Q#3		; A ADDRESSES CONSTANT PROM
ABUS:	EQU	Q#4		; A FROM BUS
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; ADDED B ADDRESS BITS (B5-B4)		[16]
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
;
BINALU: EQU	B#00		; B ADDRESSES 2903 REGISTERS
BIS7051:EQU	B#01		; B ADDRESSES FIRST 29705 ADDTION
BIS7052:EQU	B#10		; B ADDRESSES SECOND 29705 ADDITION
BBUS:	EQU	B#11		; B FROM BUS
;
EJECT
; * * * * * * * * * * * * * * * * * * * * * * * *
;
; THREE ADDRESS OPERATION - THIRD ADDRESS FIELD
; ADDED C ADDRESS BITS (C5-C4)		[17]
; * * * * * * * * * * * * * * * * * * * * * * * *
;
;
CIN2903:EQU	B#00		; C ADDRESSES 2903 REGISTERS
CIS7051:EQU	B#01		; C ADDRESSES FIRST 29705 ADDITION
CIS7052:EQU	B#10		; C ADDRESSES SECOND 29705 ADDITION
CBUS:	EQU	B#11		; C TO B BUS OUT
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; I0 SOURCE SELECT FIELD REPLACES EA-I0-OEB THREE-BIT FIELD
;					[18]
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
QREGSEL:EQU	B#1		; SOURCE IS Q REGISTER
NONQREG:EQU	B#0		; SOURCE IS RAMB OR B.BUS
;
EJECT
; * * * * * * * * * * * * *  * * * * * * *
;
; MISCELLANEOUS FIELDS
;
; REGISTERS				[R]
; * * * * * * * * * * * * * * * * * * * * *
;
R0:		EQU	H#0
R1:		EQU	H#1
R2:		EQU	H#2
R3:		EQU	H#3
R4:		EQU	H#4
R5:		EQU	H#5
R6:		EQU	H#6
R7:		EQU	H#7
R8:		EQU	H#8
R9:		EQU	H#9
R10:		EQU	H#A
R11:		EQU	H#B
R12:		EQU	H#C
R13:		EQU	H#D
R14:		EQU	H#E
R15:		EQU	H#F
;
; * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; CARRY BIT (2 BITS FOR NOW)		[19]
;
; * * * * * * * * * * * * * * * * * * * * * * * * * *
;
;
CARRY:		EQU	B#01
NOCARRY:	EQU	B#00		;IMAGINATIVE!
IC:		EQU	B#10		; Cin is Cout
Z:		EQU	B#11		; Z is Cin
;
EJECT
; * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; Am2910 MICROPROGRAM CONTROLLER INSTRUCTION SET [20]
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
JZ:		EQU	H#0		; RESET STACK, MICROPC, ADDRESS
CJS:		EQU	H#1		; COND JUMP SUBROUTINE, PUSH STACK
JMAP:		EQU	H#2		; UNCOND JUMP TO MEMORY MAP (Di)
CJP:		EQU	H#3		; COND JUMP PIPELINE
PUSH:		EQU	H#4		; PUSH STACK, LOAD REG MAYBE, CONT
JSRP:		EQU	H#5		; JUMP SUB FROM REG (F) OR PIPE(T)
CJV:		EQU	H#6		; COND JUMP TO VECTOR INTER (Di)
JRP:		EQU	H#7		; JUMP TO REG (F) OR PIPE (T)
RFCT:		EQU	H#8		; DO LOOP REPEAT UNTIL CTR=0 - STACK
RPCT:		EQU	H#9		; DO LOOP UNTIL CTR=0 - PIPE
CRTN:		EQU	H#A		; COND RETURN, POP STACK (T)
CJPP:		EQU	H#B		; COND JUMP PIPELINE, POP STACK
LDCT:		EQU	H#C		; LOAD REGISTER, CONTINUE
LOOP:	     EQU     H#D	     ; DO LOOP UNTIL TEST=T - STACK
CONT:		EQU	H#E		; CONTINUE
TWB:		EQU	H#F		; THREE WAY (DEAD MAN TIMER!)
;
; * * * * * * * * * * * * * * * * *
;
; Am29811 INSTRUCTION SET
;
; * * * * * * * * * * * * * * * * *
;
; NOTE: THE SAME AS THE Am2910 EXCEPT TWB IS REPLACED BY JP
; AND ALL TESTS ARE ACTIVE HIGH RATHER THAN ACTIVE LOW
;
JP:		EQU	H#F		; UNCONDITIONAL JUMP PIPELINE
;
;
; EXAMPLE SEQUENCER SUB STATEMENT
;
SEQR:	 SUB	4VH#E, 3VQ#0,  12V$X	;
;		INSTR  MUX     ADDR
;		CONT	?      #
;
;
;
EJECT
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; Am2925 CYCLE LENGTH SELECT			[21]
; System Clock Generator and Driver
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; THE FOLLOWING ARE THE CYCLE LENGTH CODES  (PRELIM)
;							EXAMPLE CYCLE (1 OF 4)
CLA:	EQU	Q#0	; 3 CLOCK PERIODS		100ns AT 30MHz
CLB:	EQU	Q#1	; 4				160ns AT 25MHz
CLC:	EQU	Q#5	; 5				200ns AT 25MHz
CLD:	EQU	Q#7	; 6				200ns AT 30MHz
CLE:	EQU	Q#3	; 7				280ns T 25MHz
CLF:	EQU	Q#2	; 8				320ns AT 25MHz
CLG:	EQU	Q#6	; 9				300ns AT 30MHz
CLH:	EQU	Q#4	; 10 CLOCK PERIODS		322ns AT 31MHz
;					(max crystal frequency is 311MHz)
;
; OTHER CONTROL LINES FOR THE Am2925
; INCOMPLETELY DEFINED AT PRESENT (IN THIS FILE)
;
FIRST.25:	EQU	B#1		;
LAST.25:	EQU	B#0		;
;
HALT:		EQU	B#00		;
NOHALT: 	EQU	B#00		;
;
SINGLSTP:	EQU	B#00		;
RUN:		EQU	B#00		;
;
WAITREQ:	EQU	B#0		;
NOWAITQ:       EQU     B#1	       ;
;
READY:		EQU	B#0		;
NOTREADY:	EQU	B#1		;
;
INITIALIZE:	EQU	B#0		;
NO.INIT:	EQU	B#1		;
;
EJECT
; * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; Am2904 SHIFT INSTRUCTIONS (I9-I8-I7-I6 AND SE)
;    I10 IS TIED TO I8 OF Am2903/29203
;
; * * * * * * * * * * * * * * * * * * * * * * * * * *
;
;
; DOWN SHIFTING
;
SDZRZQ: 	EQU	H#0		; Z->RN; Z->QN
SDOROQ: 	EQU	H#1		; 1->RN; 1->QN
SLN.RECOVER:	EQU	H#2		; 0->RN; R0->Mc; MN->QN
DDOR:		EQU	H#3		; 1->RN; R0->QN
DDMCR:		EQU	H#4		; Mc->RN; R0->QN
DLN.RECOVER:	EQU	H#5		; MN->RN; R0->QN
DDZR:		EQU	H#6		; 0->RN; R0->QN
DDZRQMC:	EQU	H#7		; 0->RN; R0->QN; Q0->Mc
SDROTMC:	EQU	H#8		; ROT.R; R0->Mc; ROT.Q
SDROTC: 	EQU	H#9		; ROT.R WITH Mc; ROT.Q
SDROT:		EQU	H#A		; ROT.R; ROT.Q
SDIC:		EQU	H#B		; Ic->RN; R0->QN
DDROTC: 	EQU	H#C		; Mc->RN; R0->QN; Q0->Mc
DDROTMC:	EQU	H#D		; Q0->RN; R0->QN; Q0->Mc
DDINIOVR:	EQU	H#E		; IN EXOR IOVR -> RN; R0->QN
DDROT:		EQU	H#F		; DOUBLE PRECISION ROTATE DOWN
;
; UP SHIFTING (INCOMPLETE)
;
SURZQZ: 	EQU	H#2		; R0<-0; Q0<-0
;
; SHIFT ENABLES
;
SE.EN:		EQU	B#0		; ENABLE SHIFTING
SE.DIS: 	EQU	B#1		; DISABLE SHIFTING
EJECT
;
;
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
; Am2904 STATUS REGISTER INSTRUCTION CODES
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
; MACHINE STATUS REGISTER INSTRUCTION CODES
;    I5-I4-I3-I2-I1-I0 AND EZ-EC-EN-EOVR-CEM ENABLES
; MICRO STATUS REGISTER INSTRUCTION CODES
;    I5-I4-I3-I2-I1-I0 AND CEu ENABLE
;
; THE FOLLOWING TAKES THESE ALL TOGETHER - YOU MAY WISH TO DO THIS ANOTHER WAY
;
; ORDER: 543 210 ZCNOVR CEM CEu
;	 Q#  Q#  H#	B#  B#
;
ONELEVEL:	EQU	12Q#0000	; Y -> MSR; MSR -> USR
SET.MSR:	EQU	12Q#0101	; SET MACRO STATUS ONLY
SET.USR:	EQU	12Q#0176	; SET MICRO STATUS ONLY
SWAP.REG:	EQU	12Q#0200	; MSR <--> USR
;
LOAD.MSR:	EQU	12Q#2001	; ALU STATUS -> MSR
; THE ABOVE IS ONE OF SEVERAL CODES - YOU DON'T NEED THEM ALL!
;
LOAD.USR:	EQU	12Q#2076	; ALU STATUS -> USR
; DITTO!
;
LOAD.BOTH:	EQU	12Q#2000	; ALU -> MSR,
; AGAIN DITTO!
;
LDINVRTM:	EQU	12Q#3001	; ALU -> MSR; Ic INVERTED
LDINVRTU:	EQU	12Q#3076	; ALU -> USR; Ic INVERTED
LOAD.INVERT:	EQU	12Q#3000	; ALU -> MSR, USR; Ic INVERTED
;
EJECT
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
; Am2904 CONDITION CODE OUTPUT INSTRUCTION CODES
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
; caution!  I5-I4-I3-I2-I1-I0 ARE ALSO USED FOR TESTING!!!!
; ENABLE TESTING VIA OEct ENABLE
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
TESTMZ: 	EQU	12Q#477        ; NO STATUS OPERATION
TESTMOVR:	EQU	12Q#4677	; NO STATUS OPERATION
TESTMC: 	EQU	12Q#5277	; NO STATUS OPERATION
TESTMN: 	EQU	12Q#5677	;
TEST.IOVR:	EQU	12Q#6677	;
TEST.IC:	EQU	12Q#7277	;
;
;
; TEST ENABLE
;
OECTEN: 	EQU	B#0
OECTDIS:	EQU	B#1
;
;
; OUTPUT ENABLE
;
OEYEN:		EQU	B#0
OEYDIS: 	EQU	B#1
;
; INSTRUCTION ENABLE
;
IEN:		EQU	B#0
IENDIS: 	EQU	B#1
;
;
; CONDITIONAL CODE MULTIPLEXER (DATA MONITOR)
;
NOACK:		EQU	Q#0
COUT:		EQU	Q#1
PASS:		EQU	Q#7
;
EJECT
;
; Certain of the EQU groupings are labeled by [i].  The following DEF statements
; are documented by referring to the group of mnemonics which may be substituted
; in the various variable fields.  The reference is via [i].  The DEF statements
; are also documented by providing a comment on the default value given.
;
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
; Am2901-BASED CPU
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
AM2901:  DEF 19X, 3VQ#1, 3VQ#0, 3VQ#1, 2VB#00, 4VH#0, 4VH#0, 26X
; DEFAULTS	   AB	 ADD.01 NOP.01	NOCin  R0     R0
;		   [1]	  [2]	 [3]	[19]   [R]    [R]
;
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
; Am29203/2903 TWO ADDRESS OPERATION - NO EXPANDED MEMORY
; * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
;
AM29203: DEF 19X, 3VQ#0, 4VH#F, 4VH#C, 2VB#00, 4VH#0, 4VH#0, 1VB#0, 1VB#0, 22X
; DEFAULTS	  RAMAB  OR	YBUS   NOCin   R0     R0     IEN    OEY.EN
;		  [9]	 [13]	[11]   [19]    [R]    [R]
;				[14]
;
AM2903:  DEF 19X, 3VQ#0, 4VH#F, 4VH#C, 2VB#00, 4VH#0, 4VH#0, 1VB#0, 1VB#0, 22X
;  DEFAULTS	  RAMAB  OR	YBUS   NOCin   R0     R0     IEN    OEY.EN
;		  [9]	 [10]	[11]   [19]    [R]    [R]
;				[12]
;
AM2910:   DEF	4VH#E, 3VX, 12V$X, 45X
; DEFAULTS	CONT   #    #
;		[20]
;
;
; note: This file is written such that the AM2910, AM29203, and AM2904 DEF
; statements are overlayed in the .SRC file.  The user would add additional DEF
; definitions for his/her additional fields in the microword.  Or, the user can
; delete all DEF statements and begin anew.  The intent of this file and all
; other MASTER files s to help reduce the effort required in using AMDASM by
; reducing the effort required to create a customized .DEF file.
;
EJECT
;
;
; ADDITIONAL EXAMPLE DEF STATEMENTS
;
;
AM2904:   DEF	42X,	12VQ#2001, 1VB#1,  1VB#0, 4VX,	1VB#1, 3X
; DEFAULTS		LOAD.MSR   OECTDIS OEYEN  X	SE.DIS
;
SHIFT:	  DEF	56X,  4VX, 1B#0, 3X
;		      SHIFT SE.EN
TEST:	  DEF	42X, 12VQ#7777, 1VB#0, 9X
;		     DISABLED	OECTEN
STATUS:   DEF	42X, 12VQ#2001, B#1, 1VB#0, 4X, B#1, 3X
;		     LOAD.MSR  NO CT OEYEN     SE.DIS
;
; *********************************************************************
; ADDED STATEMENTS FOR DATA MONITOR PROBLEM - USES Am2903 sans .03 **
; ( This is for the EDSYS29 class - other users should delete )
; *********************************************************************
;
NOP2903:  DEF	19X, Q#0, H#F, H#C, B#00, H#0, H#0, B#0, B#1, 22X
;
CTRL:	  DEF	61X, 1VB#0, 1VB#0, 1VB#0
;		     DATAin DATAout MEMORY MAP SELECT
;		     CTRL   CTRL    FIRST QUADRANT
END
