TITLE AM29116 / AM9520 DISK CONTROLLER 9/81 Tabler-Kitson
;
; This .DEF file (DISKCTLR.DEF) was created by editing CONTROLR.DEF;
; by adding DEF and EQU statements, deleting some others, and by
; changing the basic microword format.	The bulk of the effort required
; to create such a file was considerably reduced by beginning from the
; "master" file (CONTROLR.DEF) rather than typing a new file from scratch.
;
; This particular .DEF file was created for a specific Am29116-Am9520
; disk controller, described in the AMD application note:
; "A High-Performance Intelligent Disk Controller," by Otis Tabler and
; Brad Kitson, to be released by AMD in early 1982.  The source file
; is DISKCTLR.SRC.
;
; The major difference between this DEF file and the CONTROLR.DEF file is
; the approach to the microprogramming.  This file makes heavy use of
; DEF statement overlays while the other uses the comma-positional
; notation.  The choice is a matter of preference. THE Am29116 MNEMONICS
; AND INSTRUCTION LAYOUT ARE IDENTICAL IN THESE FILES.
;
;
; This file may also be used as a master file which the user can edit to
; suit his/her application.
;
; Anyone finding an error in this file is requested to send a marked listing
; or portion thereof to: AMD APPLICATIONS     or  AMD CUSTOMER EDUCATION CENTER
;			 PO BOX 453  MS#70	  POBOX 453  MS#71
;			 SUNNYVALE, CA 94086	  490-A LAKESIDE DRIVE
;						  SUNNYVALE, CA 94086
;
; Advanced Micro Devices reserves the right to make changes in its product
; without notice in order to improve design or performance characteristics.
; The company assumes no responsibility for the use of any circuits or
; programs described herein.
;
;
; Am29116 Mnemonics Copyright  c  1982 Advanced Micro Devices, Inc.
;
;
EJECT
;
;
WORD	80
;
; *************************************************
; GENERAL MNEMONICS
; *************************************************
;
; BYTE - WORD MODE SELECT [M] <----------ferenced by DEF statements
;
B:		EQU		1B#0	; BYTE MODE
W:		EQU		1B#1	; WORD MODE
;
;
; *************************************************
; N SELECT [N]
;
N0:		EQU		H#0	; 0
N1:		EQU		H#1	;
N2:		EQU		H#2	;
N3:		EQU		H#3	;
N4:		EQU		H#4	;
N5:		EQU		H#5	;
N6:		EQU		H#6	;
N7:		EQU		H#7	;
N8:		EQU		H#8	;
N9:		EQU		H#9	;
NA:		EQU		H#A	;
NB:	       EQU	       H#B     ;
NC:		EQU		H#C	;
ND:		EQU		H#D	;
NE:		EQU		H#E	;
NF:		EQU		H#F	;
EJECT
;
; ***************************************************
; 32 RAM REGISTERS [R]
;
R0:		EQU		5D#0	; 00000
R1:		EQU		5D#1	;
R2:		EQU		5D#2	;
R3:		EQU		5D#3	;
R4:		EQU		5D#4	;
R5:		EQU		5D#5	;
R6:		EQU		5D#6	;
R7:		EQU		5D#7	;
R8:		EQU		5D#8	;
R9:		EQU		5D#9	;
R10:		EQU		5D#10	;
R11:		EQU		5D#11	;
R12:		EQU		5D#12	;
R13:		EQU		5D#13	;
R14:		EQU		5D#14	;
R15:		EQU		5D#15	;
R16:		EQU		5D#16	;
R17:		EQU		5D#17	;
R18:		EQU		5D#18	;
R19:		EQU		5D#19	;
R20:		EQU		5D#20	;
R21:		EQU		5D#21	;
R22:		EQU		5D#22	;
R23:		EQU		5D#23	;
R24:		EQU		5D#24	;
R25:		EQU		5D#25	;
R26:		EQU		5D#26	;
R27:		EQU		5D#27	;
R28:		EQU		5D#28	;
R29:		EQU		5D#29	;
R30:	     EQU	     5D#30   ;
R31:		EQU		5D#31	;
;
EJECT
;
;
; *****************************
; SINGLE OPERAND INSTRUCTIONS
; *****************************
;
; OPCODES [1]
;
MOVE:		EQU		H#C	; 1100 MOVE
COMP:		EQU		H#D	; 1101 COMP
INC:		EQU		H#E	; 1110 INC     INCREMENT
NEG:		EQU		H#F	; 1111 NEG     INCREMENT COMP
;
; SOURCE-DESTINATION SELECT [2]
;
SORA:		EQU		H#0	; RAM	ACC
SORY:		EQU		H#2	; RAM	Y BUS
SORS:		EQU		H#3	; RAM	STATUS
SOAR:		EQU		H#4	; ACC	RAM
SODR:		EQU		H#6	; D	RAM
SOIR:		EQU		H#7	; I	RAM
SOZR:		EQU		H#8	; 0	RAM
SOZER:		EQU		H#9	; D(0E) RAM
SOSER:		EQU		H#A	; D(SE) RAM
SORR:		EQU		H#B	; RAM	RAM
;
; ************************************************************
SOR: DEF 1V,  B#10,4V%D#,    4V%D#,	    5V%D#,64X	; SINGLE OPERAND RAM
;	    \		  \	  \	      \
;	       MODE,QUAD,OPCODE,SOURCE-DEST,REGISTER
;		[M]	    [1]      [2]	[R]    <---- refer to proper EQU groups
; ************************************************************
EJECT
;
; SOURCE (R/S) [3]
;
SOA:	       EQU	       H#4     ; ACC
SOD:		EQU		H#6	; D
SOI:		EQU		H#7	; I
SOZ:		EQU		H#8	; 0
SOZE:		EQU		H#9	; D(0E)
SOSE:		EQU		H#A	; D(SE)
;
; DESTINATION [4]
;
NRY:		EQU		D#0	; Y BUS
NRA:		EQU		D#1	; ACC
NRS:		EQU		D#4	; STATUS
NRAS:		EQU		D#5	; ACC,STATUS
;
; ***************************************************************
SONR:F 1V,  B#11,4V%D#,    4V%D#,    5V%D#,64X	      ; SINGLE OPERAND NON-RAM
;
;		MODE,QUAD,OPCODE,SOURCE,DESTINATION
;		[M]	    [1]    [3]	    [4]
; ***************************************************************
EJECT
;
;
;
; ***********************************
; TWO OPERAND INSTRUCTIONS
; ***********************************
;
; OPCODES [5]
;
SUBR:		EQU		H#0	; S minus R
SUBRC:		EQU		H#1	; S minus R with carry
SUBS:		EQU		H#2	; R minus S
SUBSC:		EQU		H#3	; R minus S with carry
ADD:		EQ	       H#4     ; R plus S
ADDC:		EQU		H#5	; R plus S with carry
AND:		EQU		H#6	; R . S
NAND:		EQU		H#7	; R . S
EXOR:		EQU		H#8	; R   S
NOR:		EQU		H#9	; R + S
OR:		EQU		H#A	; R + S
EXNOR:		EQU		H#B	; R   S
;
;
; SOURCE-DESTINATION [6]		; R	S	DEST
;
TORAA:		EQU		H#0	; RAM	ACC	ACC
TORIA:		EQU		H#2	; RAM	I	ACC
TODRA:		EQU		H#3	; D	RAM	ACC
TORAY:		EQU		H#8	; RAM	ACC	Y BUS
TORIY:		EQU		H#A	; RAM	I	Y BUS
TODRY:		EQU		H#B	; D	RAM	Y BUS
TORAR:		EQU		H#C	; RAM	ACC	RAM
TORIR:		EQU		H#E	; RAM	I	RAM
TODRR:		EQU		H#F	; D	RAM	RAM
;
; ************************************************************
TOR1: DEF 1V,  B#00,4V%D#,	   4V%D#,    5V%D#,64X	 ; TWO OPERAND RAM (1)
;
;		MODE,QUAD,SOURCE-DEST,OPCODE,REGISTER
;		[M]	       [6]     [5]     [R]
; ************************************************************
EJECT
;
;
; SOURCE-DESTINATION [7]		      R     S	    DEST
;
TODAR:		EQU		H#1	; D	ACC	RAM
TOAIR:		EQU		H#2	; ACC	I	RAM
TODIR:		EQU		H#5	; D	I	RAM
;
; ************************************************************
TOR2: DEF 1V,  B#10,4V%D#,	   4V%D#,    5V%D#,64X	 ; TWO OPERAND RAM (2)
;
;		MODE,QUAD,SOURCE-DEST,OPCODE,REGISTER
;		[M]	      [7]	[5]    [R]
; ***********************************************************
;
; SOURCE   [8]				     R	   S
;
TODA:		EQU		H#1	; D	ACC
TOAI:		EQU		H#2	; ACC	I
TODI:		EQU		H#5	; D	I
;
; ***********************************************************
TONR: DEF 1V,	B#11,4V%D#,    4V%D#,	 5V%D#,64X	 ; TWO OPERAND NON-RAM
;
;		MODE, QUAD,SOURCE,OPCODE,DESTINATION
;		[M]	     [8]    [5]     [4]
; ***********************************************************
EJECT
; **************************************************
; SHIFT INSTRUCTIONS
; **************************************************
;
; DIRECTION AND INPUT [9]
;
SHUPZ:		EQU		H#0	; UP 0
SHUP1:		EQU		H#1	; UP 1
SHUPL:		EQU		H#2	; UP QLINK
SHDNZ:		EQU		H#4	; DOWN 0
SHDN1:		EQU		H#5	; DOWN 1
SHDNL:		EQU		H#6	; DOWN QLINK
SHDNC:		EQU		H#7	; DOWN QC
SHDNOV: 	EQU		H#8	; DOWN QN QOVR
;
;
; SOURCE [10]
;
SHRR:		EQU		H#6	; RAM	RAM
SHDR:		EQU		H#7	; D	RAM
;
;
; *****************************************************
SHFTR: DEF 1V,	B#10,4V%D#,	    4V%D#,    5V%D#,64X  ; SHIFT RAM
;
;		MODE,QUAD,SOURCE,DIRECT-INPT,REGISTER
;		[M]	   [10]       [9]     [R]
; *****************************************************
;
;
; SOURCE [11]
;
SHA:		EQU		H#6	; ACC
SHD:		EQU		H#7	; D
;
;
; *****************************************************
SHFTNR: DEF 1V,  B#11,4V%D#,	4V%D#,	  5V%D#,64X	 ; SHIFT NON-RAM
;
;		MODE,QUAD,SOURCE,DIRECT-INP,DESTINATION
;		[M]	    [11]   [9]	      [4](NRY; NRA ONLY)
; *****************************************************
EJECT
;
; **************************************************
;ROTATE INSTRUCTIONS
; **************************************************
;
; SOURCE-DESTINATION [12]
;
RTRA:		EQU		H#C	; RAM	ACC
RTRY:		EQU		H#E	; RAM	Y BUS
RTRR:		EQU		H#F	; RAM	RAM
;
;
; *****************************************************
ROTR1: DEF  1V,  B#00,4V%D#,4V%D#,	  5V%D#,64X	 ; ROTATE RAM (1)
;
;		MODE,QUAD,N,SOURCE-DEST,REGISTER
;		[M]	 [N]	 [12]	  [R]
; *****************************************************
;
; SOURCE-DESTINATION [13]
;
RTAR:		EQU		H#0	; ACC	RAM
RTDR:		EQU		H#1	; D	RAM
;
;
; ****************************************************
ROTR2: DEF  1V,  B#01,4V%D#,4V%D#,	  5V%D#,64X	 ; ROTATE RAM (2)
;
;		MODE,QUAD,N,SOURCE-DEST,REGISTER
;		[M]	 [N]	[13]	  [R]
; *****************************************************
;
; SOURCE DESTINATION [14]
;
RTDY:		EQU		D#24	; D	Y BUS
RTDA:		EQU		D#25	; D	ACC
RTAY:		EQU		D#28	; ACC	Y BUS
RTAA:		EQU		D#29	; ACC	ACC
;
;
; *****************************************************
ROTNR: DEF  1V,  B#11,4V%D#,H#C,      5V%D#,64X  ; ROTATE NON-RAM
;
;		MOD,QUAD,N,FIXED CODE,DESTINATION
;		[M]	 [N]		   [14]
; *****************************************************
EJECT
; ***************************************************
; BIT ORIENTED INSTRUCTIONS
; ***************************************************
;
; OPCODES [15]
;
SETNR:		EQU		H#D	; SET RAM, BIT N
RSTNR:		EQU		H#E	; RESET RAM, BIT N
TSTNR:		EQU		H#F	; TEST RAM, BIT N
;
;
; ********************************************************
BOR1: DEF 1V,  B#11,4V%D#,4V%D#,   5V%D#,64X	 ; BIT ORIENTED RAM (1)
;
;		MODE,QUAD,N,OPCODE,REGISTER
;		[M]	 [N]  [15]    [R]
; ********************************************************
;
;
; OPCODES [16]
;
LD2NR:		EQU		H#C	; 2^N --- RAM
LDC2NR: 	EQU		H#D	; 2^N --- RAM
A2NR:		EQU		H#E	; RAM + 2^N - RAM
S2NR:		EQU		H#F	; RAM - 2^N - RAM
;
;
; ********************************************************
BOR2: DEF 1V,  B#10,4V%D#,4V%D#,   5V%D#,64X	 ; BIT ORIENTED RAM (2)
;
;		MODE,QUAD,N,OPCODE,REGISTER
;		[M]	 [N]  [16]    [R]
; ********************************************************
EJECT
;
; OPCODES [17]
;
TSTNA:		EQU		D#0	; TEST ACC, BIT N
RSTNA:		EQU		D#1	; RESET ACC, BIT N
SETNA:		EQU		D#2	; SET ACC, BIT N
A2NA:		EQU		D#4	; ACC + 2^N -- ACC
S2NA:		EQU		D#5	; ACC - 2^N --ACC
LD2NA:		EQU		H#6	; 2^N -- ACC
LDC2NA: 	EQU		D#7	; 2^N -- ACC
TSTND:		EQU		D#16	; TEST D, BIT N
RSTND:		EQU		D#17	; RESET D, BIT N
SETND:		EQU		D#18	; SET D, BIT N
A2NDY:		EQU		D#20	; D + 2^N -- Y BUS
S2NDY:		EQU		D#21	; D - 2^N -- Y BUS
LD2NY:		EQU		D#22	; 2^N -- Y BUS
LDC2NY: 	EQU		D#23	; 2^N -- Y BUS
;
;
; *********************************************************
BONR: DEF 1V,  B#11,4V%D#,B#1100,    5V%D#,64X	 ; BIT ORIENTED NON-RAM
;
;		MODE,QUAD,N,FIXED CODE,OPCODE
;		[M]	 [N]		[17]
; *********************************************************
EJECT
; **************************************************
; ROTATE AND MERGE
; **************************************************
;
; SOURCE-DEST SELECT [U,S,MASK-DEST] [18]
;
;					  ROT	NON-ROT  MASK-DEST
MDAI:		EQU		H#7	; D	ACC	I
MDAR:		EQU		H#8	; D	AC     RAM
MDRI:		EQU		H#9	; D	RAM	I
MDRA:		EQU		H#A	; D	RAM	ACC
MARI:		EQU		H#C	; ACC	RAM	I
MRAI:		EQU		H#E	; RAM	ACC	I
;
;
; **********************************************************
ROTM: DEF 1V,  B#01,4V%D#,4V%D#,	5V%D#,64X	 ;ROTATE AND MERGE
;
;		MODE,QUAD,N,SOURCE-DEST,REGISTER
;		[M]	 [N]	[18]	   [R]
; **********************************************************
;
; ***********************************************
; ROTATE AND COMPARE
; **************************************************
;
; ROT.SRC(U)-NON ROT.SRC(S)/DEST-MASK(S)[19]
;
CDAI:		EQU		H#2	; D	ACC	I
CDRI:		EQU		H#3	; D	RAM	I
CDRA:		EQU		H#4	; D	RAM	ACC
CRAI:		EQU		H#5	; RAM	ACC	I
;
;
; ********************************************
ROTC: DEF 1V,  B#01,4V%D#,4V%D#,	     5V%D#,64X	 ; ROTATE AND COMPARE
;
;		MODE,QUAD,N,SOURCE-DEST-MASK,REGISTER
;		[M]	 [N]	   [19]        [R]
; *********************************************
EJECT
; **************************************************
; PRIORITIZE
; **************************************************
;
; SOURCE [20]
;
PRT1A:		EQU		H#7	; ACC
PR1D:		EQU		H#9	; D
;
;
; DESTINATION [21]
;
PR1A:		EQU		H#8	; ACC
PR1Y:		EQU		H#A	; Y BUS
PR1R:		EQU		H#B	; RAM
;
; ***********************************************
PRT1: DEF 1V,  B#10,4V%D#,	      4V%D#,	5V%D#,64X	 ; RAM ADDR MASK(S)
;
;		MODE,QUAD,DESTINATION,SOURCE,REG-MASK
;		[M]	      [21]     [20]    [R]
; ***********************************************
;
;
; DESTINATION [23]
;
PR2A:		EQU		H#0	; ACC
PR2Y:		EQU		H#2	; Y BUS
;
; MASK (S) [22]
;
PRA:		EQU		H#8	; ACC
PRZ:		EQU		H#A	; 0
PRI:		EQU		H#B	; I
;
;
; ***********************************************
PRT2: DEF 1V,  B#10,4V%D#,  4V%D#,  5V%D#,64X	 ; PRIORITIZE RAM
;
;		MODE,QUAD,MASK,DEST,REG-SOURCE
;		[M]	  [22] [23]    [R]
; ***********************************************
EJECT
; SOURCE (R) [24]
;
PR3R:		EQU		H#3	; RAM
PR3A:		EQU		H#4	; ACC
PR3D:		EQU		H#6	; D
;
;
; ***********************************************
PRT3: DEF 1V,  B#10,4V%D#,  4V%D#,    5V%D#,64X  ; PRIORITIZE RAM
;
;		MODE,QUAD,MASK,SOURCE,REG-DEST
;		[M]	  [22]	[24]	[R]
; **********************************************
;
;
; SOURCE (R) [25]
;
PRTA:		EQU		H#4	; ACC
PRTD:		EQU		H#6	; D
;
;
; **********************************************
PRTNR: DEF  1V,  B#11,4V%D#,  4V%D#,	5V%D#,64X	 ; PRIORITIZE NON-RAM
;
;		   MODE,QUAD,MASK,SOURCE,DESTINATION
;		   [M]	     [22]  [25]    [4](NRY,NRA ONLY)
; **********************************************
EJECT
;
; **********************************************
; CYCLIC REDUNDANCY CHECK
; **********************************************
;
; *******************************************
CRCF: DEF B#11001100011,5V%D#,64X	 ; FORWARD
; *******************************************
;
; *******************************************
CRCR: DEF B#11001101001,5V%D#,64X	 ; REVERSE
; *******************************************
;
; ********************************************
;
; NOOP
;
; ********************************************
NOOP: DEF H#7140,64X	; NO OPERATION
; ********************************************
EJECT
;
; ************************************************
; STATUS
; ************************************************
;
; OPCODE [26]
;
SONZC:		EQU		5D#3	; SET OVR,N,C,Z
SL:		EQU		5D#5	; SET LINK
SF1:		EQU		5D#6	; SET FLAG 1
SF2:		U	      5D#9    ; SET FLAG 2
SF3:		EQU		5D#10	; SET FLAG 3
;
;
; **************************************************
SETST: DEF B#011,H#BA,5V%D#,64X  ; SET STATUS
;
;			   OPCODE
;			    [26]
; **************************************************
EJECT
;
; OPCODE [27]
;
RONCZ:		EQU		D#3	; RESET OVR,N,C,Z
RL:		EQU		D#5	; RESET LINK
RF1:		EQU		D#6	; RESET FLAG 1
RF2:		EQU		D#9	; RESET FLAG 2
RF3:		EQU		D10    ; RESET FLAG 3
;
;*****************************************************
RSTST: DEF B#011,H#AA,5V%D#,64X 	; RESET STATUS
;
;			    OPCODE
;			    [27]
; ****************************************************
;
; ****************************************************
SVSTR: DEF  1V,  B#10,H#7A, 5V%D#,64X	; SAVE STATUS-RAM
;
;		   MODE,QUAD,FIXED,RAM ADDRESS/DEST
;		    [M] 		[R]
; ****************************************************
;
;
;*****************************************************
SVSTNR: DEF  1V, B#11,H#7A, 5V%D#,64X	 ; SAVE STATUS NON-RAM
;
;		   MODE,QUAD,FIXED,DESTINATION
;		   [M]		  [4](NRY,NRA ONLY)
; ****************************************************
EJECT
;
; *************************************************
; TEST STATUS
; *************************************************
;
; OPCODE (CT)
;
TNOZ:		EQU		D#0	; TEST (N OVR) + Z
TNO:		EQU		D#2	; TEST N OVR
TZ:		EQU		D#4	; TEST Z
TOVR:		EQU		D#6	; TEST OVR
TLOW:		EQU		D#8	; TEST LOW
TC:		EQU		D#10	; TEST C
TZC:		EQU		D#12	; TEST Z + C
TN:		EQU		D#14	; TEST N
TL:		EQU		D#16	; TEST LINK
TF1:		EQU	       D#18    ; TEST FLAG 1
TF2:		EQU		D#20	; TEST FLAG 2
TF3:		EQU		D#22	; TEST FLAG 3
;
;
; *****************************************************
TEST: DEF B#011,H#9A,5V%D#,64X	 ;  TEST STATUS
;
;		 FIXED,     OPCODE
;			    [CT]
; *****************************************************
EJECT
;
; added DEF and EQU statements
;********************************
;
;	IMMEDIATE OPERAND
;
IMME:	DEF	16V%D#, 64X
;
;	CT MULTIPLEXER CONTROL
;
CT:	DEF	16X, 4V%D#, 60X
NOZ:	EQU	H#0
NO:	EQU	H#1
Z:	EQU	H#2
OVR:	EQU	H#3
LOW:	EQU	H#4
C:	EQU	H#5
ZC:	EQU	H#6
:      EQU     H#7
L:	EQU	H#8
F1:	EQU	H#9
F2:	EQU	H#A
F3:	EQU	H#B
;
;	STATUS REGISTER ENABLE
;
SRE:	DEF	20X, B#1, 59X
NOSRE:	DEF	20X, B#0, 59X
;
;	OUTPUT ENABLE Y
;
OEY:	DEF	21X, B#0, 58X
NOOEY:	DEF	21X, B#1, 58X
;
;	INSTRUCTION ENABLE
;
IEN:	DEF	22X, B#0, 57X
NOIEN:	DEF	22X, B#1, 57X
;
;	D-I-LATCH ENABLE
;
DLE:	DEF	23X, B#1, 56X
NODLE:	DEF	23X, B#0, 56X
EJECT
;
;
;
;--------------------------------------------------
;     Am2910 COMMANDS AND BRANCH ADDRESSES
; note use of DEF statements - overlay in SRC file
;--------------------------------------------------
JZ:	DEF	24X, H#0, 10V$D#1023, 42X
CJS:	DEF	24X, H#1, 10V$D#1023, 42X
JS:	DEF	24X, H#1, 10V$D#1023, 6Q#36, 36X	;  UNCONDITIONAL JUMP TO SUBR.
JMAP:	DEF	24X, H#2, 10V$D#1023, 42X
CJP:	DEF	24X, H#3, 10V$D#1023, 42X
JP:	DEF	24X, H#3, 10V$D#1023, 6Q#36, 36X	;  UNCONDITIONAL JUMP
PUSH:	DEF	24X, H#4, 10V$D#1023, 42X
JSRP:	DEF	24X, H#5, 10V$D#1023, 42X
CJV:	DEF	24X, H#6, 10V$D#1023, 42X
JRP:	DEF	24X, H#7, 10V$D#1023, 42X
RFCT:	DEF	24X, H#8, 10V$D#1023, 42X
RPCT:	DEF	24X, H#9, 10V$D#1023, 42X
CRTN:	DEF	24X, H#A, 10V$D#1023, 42X
RTN:	DEF  24X, H#A, 10V$D#1023, 6Q#36, 36X	     ;	UNCONDITIONAL RETURN
CJPP:	DEF	24X, H#B, 10V$D#1023, 42X
LDCT:	DEF	24X, H#C, 10V$D#1023, 42X
LOOP:	DEF	24X, H#D, 10V$D#1023, 42X
CONT:	DEF	24X, H#E, 10V$D#1023, 42X
TWB:	DEF	24X, H#F, 10V$D#1023, 42X
;			     ^
;			     |
;			     |
; NOTE: For proper assembly, a "$" must be used in any field which
; will be used to accept a symbolic address in the SRC file.
;
;
;
EJECT
;
;
;
;
;     Am2910 CONDITION CODE SELECTIONS
;
IF:	DEF	38X, 5V%D#, B#0, 36X
IFNOT:	DEF	38X, 5V%D#, B#1, 36X
;
;
AE20:	EQU	5Q#10:		; AM9520 ALIGNMENT ERROR FLAG
CT16:	EQU	5Q#11:		; AM29116 CONDITIONAL TEST FLAG
EP20:	EQU	5Q#12:		; AM9520 ERROR PATTERN FLAG
ER20:	EQU	5Q#13:		; AM9520 ERROR DETECTED FLAG
FAIL:	EQU	5Q#14:		; UNCONDITIONAL FAILURE OF "TEST"
RDYI:	EQU	5Q#15:		; NOT READY INPUT (DATA UNAVAILABLE FROM FIFOS)
RDYO:	EQU	5Q#16:		; NOT READY OUTPUT (FIFOS FULL)
SUCC:	EQU	5Q#17:		; UNCONDITIONAL SUCCESS OF "TEST"
ATTN:	EQU	5Q#20:		; ATTENTION
BACK:	EQU	5Q#21:		; BUS ACKNOWLEDGE
BUSY:	EQU	5Q#22:		; BUSY
INDX:	EQU	5Q#23:		; INDEX
SAMD:	EQU	5Q#24:		; SECTOR / ADDRESS MARK DETECTED
PM2:	EQU	5Q#25:		; AM9520 PATTERN MATCH 2 FLAG
PM3:	EQU	5Q#26:		; AM9520 PATTERN MATCH 3 FLAG
PM4:	EQU	5Q#27:		; AM9520 PATTERN MATCH 4 FLAG
EJECT
;
;	MISCELLANEOUS CONTROL SIGNALS
;
ADMC:	DEF	44X, B#0, 35X	; ADDRESS MARK CONTROL
BFCB:	DEF	45X, B#0, 34X	; MEMORY BUS FROM DRIVE CONTROL BUS
BFTP:	DEF	46X, B#0, 33X	; MEMORY BUS FROM TRANSLATE PROM
BF03:	DEF	47X, B#0, 32X	; MEMORY BUS FROM 9403AS
BF16:	D     48X, B#0, 31X   ; MEMORY BUS FROM AM29116
BF2L:	DEF	49X, B#0, 30X	; MEMORY BUS FROM AM9520 - LOWER BYTE
BF2U:	DEF	50X, B#0, 29X	; MEMORY BUS FROM AM9520 - UPPER BYTE
BOUT:	DEF	51X, B#0, 28X	; (DISK) BUS DIRECTION OUT (FROM CONTROLLER)
BT03:	DEF	52X, B#0, 27X	; MEMORY BUS TO 9403AS
BT16:	DEF	53X, B#0, 26X	; MEMORY BUS TO AM29116
BT2L:	DEF	54X, B#0, 25X	; MEMORY BUS TO AM9520 - LOWER BYTE
BT2U:	DEF	55X, B#0, 24X	; MEMORY BUS TO AM9520 - UPPER BYTE
BT20:	DEF	56X, B#0, 23X	; MEMORY BUS TO AM9520 - CONTROL INFORMATION
CE2L:	DEF	57X, B#0, 22X	; CLOCK ENABLE AM9520 TO LOWER-BYTE BUS INT.
CE20:	DEF	58X B#0, 21X   ; CLOCK ENABLE MEMORY BUS TO AM9520 TRANSFER
CP20:	DEF	59X, B#0, 20X	; CLOCK PULSE (ACTUAL WAVEFORM) FOR AM9520
CREQ:	DEF	60X, B#0, 19X	; COMMAND REQUEST
INPT:	DEF	61X, B#0, 18X	; INPUT SERIAL DATA TO 9403AS
JMPI:	DEF	62X, B#01, 16X	; JUMP INDIRECT AM29116 REGISTER
NOJMPI: DEF	62X, B#10, 16X	; NO INDIRECT JUMP
MADR:	DEF	64X, B#0, 15X	; MEMORY ACCESS
MREA:	DEF	65X, B#0, 14X	; MEMORY ADDRESS
MWRT:	DEF	66X, B#0, 13X	; MEMORY WRITE
OUPT:	DEF	67X, B#0, 12X	; OUTPUT SERIAL DATA FROM 9403AS
PENB:	DEF	68X, B#0, 11X	; PARAMETER ENABLE
PFPM:	DEF	69X, B#0, 10X	; SET 9520 P BITS FRM 9520 PM BITS
PF03:	DEF	70X, B#0, 9X	; PARALLEL FETCH FROM 9403AS
PL03:	DEF	71X, B#0, 8X	; PARALLEL LOAD INTO 9403AS
PREQ:	DEF	72X, B#0, 7X	; PARAMETER REQUEST
RDGA:	DEF	73X, B#0, 6X	; READ GATE
RFIF:	DEF	74X, B#0, 5X	; RESET FIFO
SAST:	DEF	75X, B#0, 4X	; SELECT / ATTENTION STROBE
WRGA:	DEF	76X, B#0, 3X	; WRITE GATE
;
ASCEBC: EQU	Q#0		; ASCII TO EBCDIC SUBSET PREFIX
BCDEBC: EQU	Q#1		; BCD TO EBCDIC SUBSET PREFIX
EBCASC: EQU	Q#2		; EBCDIC SUBSET TO ASCII PREFIX
EBCBCD: EQU	Q#3		; EBCDIC SUBSET TO BCD PREFIX
;
XLAT:	DEF	77X, 3V%D#	; TRANSLATE PREFIX
;
;
	END
