NAME

cpu — HP PA-RISC CPU

SYNOPSIS

cpu* at mainbus0 irq 31

DESCRIPTION

The following table lists the PA-RISC CPU types and their characteristics, such as TLB, maximum cache sizes and HP 9000/700 machines they were used in (see also intro(4) for the reverse list).

CPU:PA:Clock:Caches:TLB:BTLB:Models
: :(max):(max) : : :
: : MHz : KB : : :

7000:1.1a:66 : 256 L1I:96I:4 I:705,710,720
: : : 256 L1D:96D:4 D:730,750
7100:1.1b:100:1024 L1I:120:16:715/33/50/75
: : :2048 L1D: : :725/50/75
: : : : : :{735,755}/100
: : : : : :742i, 745i, 747i
7150:1.1b:125:1024 L1I:120:16:{735,755}/125
: : :2048 L1D: : :
7100LC:1.1c:100: 1 L1I:64:8:712/60/80/100
: : :1024 L2I: : :715/64/80/100
: : :1024 L2D: : :715/100XC
: : : : : :725/64/100
: : : : : :743i, 748i
: : : : : :SAIC
7200:1.1d:140: 2 L1 :120:16:C100,C110
: : :1024 L2I: : :J200,J210
: : :1024 L2D: : :
7300LC:1.1e:180: 64 L1I:96:8:A180,A180C
: : : 64 L1D: : :B132,B160,B180
: : :8192 L2: : :C132L,C160L
: : : : : :744, 745, 748
: : : : : :RDI PrecisioBook

FLOATING-POINT COPROCESSOR

The following table summarizes available floating-point coprocessor models for the 32-bit PA-RISC processors.

FPU	Model

Indigo
Sterling I MIU (TYCO)
Sterling I MIU (ROC w/Weitek)
FPC (w/Weitek)
FPC (w/Bit)
Timex-II
Rolex	725/50, 745i
HARP-I
Tornado	J2x0,C1x0
PA-50 (Hitachi)
PCXL	712/60/80/100

SUPERSCALAR EXECUTION

The following table summarizes the superscalar execution capabilities of 32-bit PA-RISC processors.

CPU	Units	Bundles

7100	1 integer ALU	load-store/fp
	1 FP	int/fp
		branch/*
7100LC	2 integer ALU	load-store/int
	1 FP	load-store/fp
		int/fp
		branch/*
7200	2 integer ALU	load-store/int
	1 FP	load-store/fp
		int/int
		int/fp
		branch/*
7300LC	2 integer ALU	load-store/int
	1 FP	load-store/fp
		int/fp
		branch/*

In conclusion, all of the above CPUs are dual-issue, or 2-way superscalar, with the exception that on CPUs with two integer ALUs only one of these units is capable of doing shift, load/store, and test operations. Additionally, there are several kinds of restrictions placed upon the superscalar execution:

For the purpose of showing which instructions are allowed to proceed together through the pipeline, they are divided into classes:

Class	Description

flop	floating point operation
ldst	loads and stores
flex	integer ALU
mm	shifts, extracts and deposits
nul	might nullify successor
bv	BV, BE
br	other branches
fsys	FTEST and FP status/exception
sys	system control instructions

For CPUs with two integer ALUs (7100LC, 7200, 7300LC), the following table lists the instructions which are allowed to be executed concurrently:

First	Second instruction

flop	+ ldst/flex/mm/nul/bv/br
ldst	+ flop/flex/mm/nul/br
flex	+ flop/ldst/flex/mm/nul/br/fsys
mm	+ flop/ldst/flex/fsys
nul	+ flop
sys	never bundled

ldst + ldst is also possible under certain circumstances, which is then called "double word load/store".

The following restrictions are placed upon the superscalar execution:

An instruction that modifies a register will not be bundled with another instruction that takes this register as operand. Exception: a flop can be bundled with an FP store of the flop's result register.
An FP load to one word of a doubleword register will not be bundled with a flop that uses the other doubleword of this register.
A flop will not be bundled with an FP load if both instructions have the same target register.
An instruction that could set the carry/borrow bits will not be bundled with an instruction that uses carry/borrow bits.
An instruction which is in the delay slot of a branch is never bundled with other instructions.
An instruction which is at an odd word address and executed as a target of a taken branch is never bundled.
An instruction which might nullify its successor is never bundled with this successor. Only if the successor is a flop instruction is this bundle allowed.

PERFORMANCE MONITOR COPROCESSOR

The performance monitor coprocessor is an optional, implementation-dependent coprocessor which provides a minimal common software interface to implementation-dependent performance monitor hardware.

DEBUG SPECIAL UNIT

The debug special function unit is an optional, architected SFU which provides hardware assistance for software debugging using breakpoints. The debug SFU is currently defined only for Level 0 processors.

HISTORY

The cpu driver was written by Michael Shalayeff <mickey@openbsd.org> for the HPPA port for OpenBSD 2.5. It was ported to NetBSD 1.6 by Matthew Fredette.